Design, Implementation, and Analysis of a Reduced Crossbar

The crossbar is the fastest switching architecture available but is the most expensive in terms of hardware cost. The hardware complexity of a crossbar is θ (nw), where n is the number of processors and w is the width of the data path. The reduced crossbar is a new type of switching architecture, which reduces the hardware complexity of a traditional crossbar by a factor of k, where k is the reduction factor. This paper focuses on the design, implementation and analysis of 16x16-reduced crossbar. Additional features such as miss handling; two-way reduction and history-based priority arbitration for the processors have been incorporated to make the crossbar more efficient. The approach is based on cache-like connectivity table, which controls the re-configurable data path of the reduced crossbar. A hit in the connectivity table transfers the data immediately while a miss costs one clock-cycle penalty. Temporal and spatial locality principles have been made use of to build the connectivity table. At any given point of time only eight connections are allowed for each processor. Least Recently Used Algorithm is used to update the connectivity table to have eight connections at all times for each processor.